The process of designing an electronic circuit can be broadly divided into two stages, a pre-layout design stage and a post-layout design stage. Examples of the design process of an electronic circuit may include, but are not limited to designing of Integrated Circuits (IC), Printed circuit Boards (PCB), Micro Electro Mechanical Systems (MEMS), and Multi Chip Modules (MCM).
The pre-layout design stage includes transforming a circuit design into a physical layout data. The physical layout data includes details of the physical locations of the circuit elements. Further, in the post-layout design stage, the physical layout data is converted into geometrical layout design data. The geometrical layout design data is used for manufacturing the electronic circuit.
The post-layout design stage includes processing of large geometrical layout design data. Processing of such data may take a significant computation overhead. Some existing methods use parallel processing of the geometrical layout design data to ensure efficient and accurate processing of the geometrical layout design data, for example, using a network of computing devices. In some methods, in a computation network, a server partitions the geometrical layout design data and transmits one or more partitions to one or more computing devices in the computation network. However, such computation networks have high startup time because processing of the geometrical layout design data starts only after the server partitions the geometrical layout design data. This results in an inefficient utilization of processing resources of computing devices. Additionally, as partitions are transmitted to computing devices at the same time, therefore, this may result in clogging of the computation network and increase the load on the server.
In some existing techniques for processing geometrical layout design data server sends the complete geometrical layout design data to each computing device. Thereafter, each computing device extracts the corresponding partition from the geometrical layout design data. However, this results in clogging of the network, as the geometrical layout design data, which is very huge in size, is transmitted to each computing device. Moreover, as the geometrical layout design data is copied on each computing device in the computation network, therefore, this leads to duplication of geometrical layout design data.
There is therefore, a need for a method and system for processing the geometrical layout design data by distributing load in an efficient manner. Further, there is a need for a method and system that has a low startup time and processes geometrical layout design data without clogging the server and the network.